The present invention relates to semiconductor devices, and more particularly to the etching of a second gate in the semiconductor device.
Semiconductor devices includes NAND-type flash memory devices. FIGS. 1A and 1B illustrate cross-sections of select transistors along a bit line in a portion of the core area of a conventional flash memory device. The select transistors include stack structures 100 and 150. The stack structures include a layer of select oxide 104 on a substrate 102 and a select gate 106 on the select oxide 104. The control gate comprises a polysilicon layer 110 and a tungsten silicide layer 112 on the polysilicon layer 110. A dielectric layer 108 insulates the select gate 106 from the control gate 110 and 112. The control gate 110 and 112 is coupled to a word line. A cap layer 114 composed of silicon oxynitride resides on the control gate 110 and 112 and provides an anti-reflective coating at masking.
To form the stack structures of the cells 100, 150, a mask and etch of the cap layers 114 and the control gates 110, 112 are performed. This etch is commonly referred to as a xe2x80x9csecond gate etchxe2x80x9d. Spacers 118 are then formed on the sides of the stack structures. The gaps between the cells 100, 150 are filled by an oxide 120. To form a wordline, the select gate 106 is connected to the control gates 110, 112 via a connector 116. The connector 116 is formed by first etching a contact hole in the oxide 120. The contact hole etch removes the thin dielectric layer 108 at the bottom of the hole, exposing the select gate 106. The hole is then filled with a conductive material.
Ideally, the second gate etch removes only the cap layers 114 and control gates 112, 110. However, occasionally a second gate over etch occurs. As illustrated in FIG. 1B, the second gate over etch results in the etching of the dielectric layer 108 and possibly portions of the select gate 106xe2x80x2. Such an over etch causes further portions of the select gate layer 106xe2x80x2 to be etched during the contact hole etch. The resulting select gate 106xe2x80x2 then becomes thinner than intended. Once the contact 116xe2x80x2 is formed, with a thinner select gate 106xe2x80x2, the wordline resistance is higher than intended. A higher wordline resistance slows down the device and compromises its reliability. The second over etch may also result in a complete punching through of the select gate 106xe2x80x2, such that the contact 116xe2x80x2 contacts the select oxide 104 rather than the select gate 106xe2x80x2. In this situation, the device becomes non-functioning.
Ways to monitor the second gate etch include measuring the thickness or the sheet resistance of the select gate 106xe2x80x2 after the etch, however, these ways are difficult due to the small size of the device. The area between the stack structures 100 and 150 is too small to allow a measuring instrument to measure the select gate 106xe2x80x2 thickness or sheet resistance. Another way of monitoring the second gate etch is to sample the device and observe its structure with a scanning electron microscope (SEM). However, this method requires the destruction of the device and is time-consuming. It is also an expensive process.
Accordingly, there exists a need for a method for monitoring for a second gate over etch in a flash memory device. The method should provide for monitoring without destroying the device. It should also save time and reduce costs. The present invention addresses such a need.
The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.